While PCIe 4.0 starting to hit the mainstream consumer market with AMD 3rd Gen Ryzen processors and X570 motherboards, the future PCIe 6.0 standard has hit an important development milestone. PCI-SIG, the non-profit organization which specifies these standards, announced that they are releasing the new version 0.5 draft.
The new PCIe 6.0 specification will have a data bandwidth of 64 GT/s per lane, which is two times larger than PCIe 5.0 (32 GT/s) and four times more than PCIe 4.0 (16 GT/s). In a PCIe 6.0×16 configuration, the total bandwidth will be about 256 GB/s. PAM-4 (Pulse Amplitude Modulation with 4 levels) encoding is implemented to pack more bits into each serial channel at the same amount of time.
The PCIe 6.0 standard will be backward compatible with all older PCI-Express generations. PCI-SIG is expected to release the more comprehensive version 0.7 draft to the public at the Developers Conference in June 2020. The final version 1.0 should be ready in 2021.
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